The present invention relates to a field effect transistor having a structure useful for an opto-electronic integrated circuit device, an opto-electronic integrated circuit device including the field effect transistor, and a method of manufacturing the same.
Generally, in manufacturing a field effect transistor (FET), the size of a gate region must be precisely controlled to satisfy specification requirements. For example, in a Schottky-gate FET (MESFET) using a compound semiconductor, the gate length and channel thickness, in addition to the carrier concentration of a channel region, greatly affect characteristics such as pinch-off voltage and transconductance.
In one conventional MESFET structure, a recess is formed in a gate region of a semiconductor layer formed on a semi-insulating semiconductor substrate, and a gate electrode is buried in this recess (recessed gate structure). In order to obtain this MESFET, a semiconductor layer is grown on a substrate and is then selectively etched to form a recess, and a gate electrode is buried in the recess. In order to obtain the desired characteristics in such a MESFET structure, the thickness of semiconductor layer in the recess region serving as a channel region and the width of the recess as a gate length must be precisely controlled. Pinch-off voltage Vp of FET is generally given by the following equation: EQU V.sub.p =.phi..sub.b -qN.sub.D A.sup.2 /2.epsilon..epsilon..sub.0
where .phi..sub.b is the barrier height of a Schottky junction; q, the electron charge; A, the channel thickness; N.sub.D, the carrier concentration of the channel region; .epsilon., the relative dielectric constant; and .epsilon..sub.0, dielectric constant in a vacuum. When an n-type InP layer with a carrier concentration of 1.times.10.sup.17 /cm.sup.3 is used as a channel layer, in order to set the pinch-off voltage to be V.sub.p =-0.7 V, the channel thickness must be set at A=0.128 .mu.m, assuming that .phi..sub.b =0.5 V and .epsilon.=12.4. In order to restrict variations in V.sub.p within .+-.0.1 V, channel thickness A must be adjusted to be within a range of .+-.55 .ANG.. It is difficult to restrict the variations in channel thickness within such a small range by the conventional method, which sets channel thickness A by controlling an etching depth, as described above.
On the other hand, the gate length must be controlled to be a small value of, e.g., 1 .mu.m to increase transconductance gm. It is also difficult to control the width of the recess, which determines the gate length, to be such a small value.
Recently, an opto-electronic integrated circuit device (OEIC) obtained by integrated an electronic device and an optical device on a single substrate is attracting a great deal of attention. It is preferred to arrange electronic and optical devices as a monolithic IC in terms of simplification in an assembly process for improvement in reliability and yield. In addition, if the above devices are arranged as a monolithic IC, excessive wiring can be reduced, resulting in a reduction of parasitic inductance or parasitic capacitance. This is advantageous for a high speed operation.
However, a conventional OEIC does not coordinate integration effectively because electronic and optical devices are merely formed on a single substrate by independent manufacturing processes. For example, in a semiconductor laser, an active layer width must be set to be about 1 .mu.m to obtain a steady transverse mode control and a low threshold current value. Therefore, when the above-mentioned FET and the semiconductor laser are to be integrated on a single substrate, extreme precision is required as to the sizes for both the devices. It is difficult to form these devices on a single substrate by independent processes to obtain a required size precision for both the devices. This is because mask alignment is difficult, since the layer structure of each device is different. Further, if these devices are formed in independent processes, many manufacturing processes are required as a whole, resulting in poor yield and high cost of an OEIC device.